Call for Papers
Download text version of the CFP
The TAP conference promotes research in verification and formal methods that targets the interplay of proofs and testing: the advancement of techniques of each kind and their combination, with the ultimate goal of improving software and system dependability.
Research in verification has recently seen a steady convergence of heterogeneous techniques and a synergy between the traditionally distinct areas of testing (and dynamic analysis) and of proving (and static analysis). Formal techniques for counter-example generation based on, for example, symbolic execution, SAT/SMT-solving or model checking, furnish evidence for the potential of a combination of test and proof. The combination of predicate abstraction with testing-like techniques based on exhaustive enumeration opens the perspective for novel techniques of proving correctness. On the practical side, testing offers cost-effective debugging techniques of specifications or crucial parts of program proofs (such as invariants). Last but not least, testing is indispensable when it comes to the validation of the underlying assumptions of complex system models involving hardware and/or system environments. Over the years, there is growing acceptance in research communities that testing and proving are complementary rather than mutually exclusive techniques.
TAP's scope encompasses many aspects of verification technology, including foundational work, tool development, and empirical research. Its topics of interest center around the connection between proofs (and other static techniques) and testing (and other dynamic techniques). Papers are solicited on, but not limited to, the following topics:
- Verification and analysis techniques combining proofs and tests,
- Program proving with the aid of testing techniques,
- Deductive techniques supporting the automated generation of test vectors and oracles (theorem proving, model checking, symbolic execution, SAT/SMT solving, constraint logic programming, etc.),
- Deductive techniques supporting novel definitions of coverage criteria,
- Specification inference by deductive and dynamic methods,
- Testing and runtime analysis of formal specifications,
- Search-based technics for proving and testing,
- Verification of verification tools and environments,
- Applications of test and proof techniques in new domains, such as security, configuration management, learning,
- Combined approaches of test and proof in the context of formal certifications (Common Criteria, CENELEC, …), and
- Case studies, tool and framework descriptions, and experience
Artifact Evaluation
Authors of all accepted papers will be invited to submit (but are not required to submit) the relevant artifact for evaluation by the artifact-evaluation committee (AEC). The AEC will read the paper and evaluate the artifact on the following criteria:
- consistency with and replicability of results in the paper,
- completeness,
- documentation, and
- ease of use.
Papers with positively evaluated artifact get a functional or reusable badge on the first page of their paper and can add an appendix of 1-2 pages to their camera-ready paper. Papers with artifacts publicly available under a DOI get an availability badge on the first page of their paper.
For further details on artifact submission, please have a look at the call for artifact submissions.
